CHAPTER
1
INTRODUCTION
1.1
Introduction
Globalization and
technological advances the higher performance, the greater energy efficiency
and the greater functionality circuits are the market demands nowadays. The
higher performances are fast evaluation time or short propagation delay, low
power dissipation and higher noise immunity. Asynchronous circuits have the
advantages of low power, faster evaluation time, higher noise immunity and low
radiation power. Asynchronous circuits are having a more complex circuit design
than synchronous circuits. However, the complexity of the circuit is necessary
in order to make the circuits have high reliability, its design is more
flexible, clock free and greater speed. Furber study’s the complexity circuit design,
produce the circuits have low power and high performance aptitude [1].
Table 1.1: Truth Table of C-element
|
Input (A)
|
Input (B)
|
Output (C)
|
|
0
|
0
|
0
|
|
0
|
1
|
Cn-1
|
|
1
|
0
|
Cn-1
|
|
1
|
1
|
1
|
The C - element is one of the most frequently used in
asynchronous circuit design [1]. The C-element is also known as C-gate or
Hyteresis flip-flop which is commonly used in VLSI design. Its output is SET
only when its input all is ‘1’ and if its input all is ‘0’, then its output is
RESET. While, all the other combinations of input will result unchanged to its
output.
C-element present best speed, energy and leakage cost
benefits when operating near the threshold voltage or near the subthreshold
regimes [2]. This kind of circuits called subthreshold circuits which having
supply voltage VDD less than the threshold voltage VTH of
the MOS transistor. However, power is proportionally changed when the change of
supply voltage. Means, reduce the supply voltage will lead to the drastic drop
in both power and energy consumption. Hence, subthreshold logic only suitable
for applications which are ultra-low power consumption, but doesn’t require
high performance [3]. The applications with subthreshold logic have longer
battery lifetime.
There are many types of
C-element which the most common transistor topologies are static, dynamic, weak-feedback
(Martin), conventional (Sutherland), symmetric (van-Berkel) and asymmetric
C-elements. This project will investigate the three parameters that will affect
the power and speed of 2 inputs C-elements. First is the voltage source VDD
applied. Compare the different supply voltage to obtain the ideal voltage for
the best performance. Second is the W/L ratio, which is the channel width to
length ratio. Third parameter will be considered is the load capacitance.
Simulation and investigation will be done by using different parameters to
obtain the optimum outcome.
1.2 Objectives
i)
To
study and analyze the each characteristic of different configurations of
C-elements. C-elements are implemented by using CMOS transistors.
ii)
To
investigate and compare the performance of different types of C-elements in
terms of speed (propagation delay) and power dissipation.
iii)
To
design the circuit with implementation of C-elements by changing its
parameters. The parameters will be tested are the size of transistors, supply
voltage and load capacitive.
iv)
To
study and investigate the operation of micropipeline.
v)
To
simulate and compare the designed circuits in terms of circuits’ performance. The
circuits will simulate and design by using LTspice.
vi)
To
layout the C-element and compare their area size by using Microwind.
vii)
To
enhance the skill of using LTspice VI and Microwind software to simulate,
analytic and layout the C-elements performances.
viii)
To
enhance the knowledge about asynchronous circuits.
ix)
To
study and investigate the application for C-element.
1.3
Problem Statement
The clock free in C-element
creates faster circuit, but at the same time, the purpose of delay is used to
hold the data before the receiver give any acknowledgement, this may cause the
deviation correctness of the circuits. Hence it is important to find a suitable
transistor sizing, voltage supply and load capacitance.
1.4
Scope of the Project
The scope of this project is to design circuits with
the implementation of different types of C-element for micropipeline and
compare their performance in terms of speed and power consumption. The
simulation tool software used is LTSpice VI to simulate and compare the
circuits.
1.5
Project Outline
Chapter 1 includes the introduction, objectives,
problem statements, scope of the projects and project outline. The introduction,
main objective is to discuss the basic concept of C-elements and the main
purpose to analyze the C-elements.
Chapter 2 describes the fundamental concept of
C-elements in terms of their theories, formulas and case studies which are
related to the C-elements. Different configuration and types of C-element will
be discussed. The basic concept of micropipeline is covered in this chapter. It
will also cover the techniques and parameters used for analysis C-element.
Chapter 3 is the methodology section which will show
the flow chart of the completion of the project, and the process of designing
the C-element, the process of simulation of the circuits. The setting of
parameters and the techniques used will discuss in this chapter.
Chapter 4 displays the result and discussion of the
project. The results of the circuits based on comparing their performance in
terms of evaluation time and power dissipation The simulation will be done by
LTspice IV.
In Chapter 5, the conclusion of the project is stated
after throughout the two semesters. Some constructive recommendations for this
project are started for further improvement.
CHAPTER 2
LITERATURE REVIEW
2.1
C-element background
C-element devised by David E. Muller
[4]. The C-element (also known as Muller
C-element or C-gate) are considerably used in the asynchronous VLSI design acts
as an events synchronizer and a state-holding element [5]. Nowadays, more than 500 new standard cells
C-element implementations [6]. Thus, it clearly stated that the C-element is
commonly efficiency used in asynchronous design in due to their higher
efficiency and lower sizing area system.
The C-element is somehow related to the JOIN or
RENDEZVOUS which JOIN is more restraining the inputs are not allowed to change
twice in succession [1]. While RENDEZVOUS element is situation the system will
not operate, unless all inputs are arrived [7]. In the experiments, C-element
is used to comprehend a JOIN or RENDEZVOUS by assuming the restrictive
environment as JOIN or RENDEZVOUS environment. C-element mostly known as
RENDEZVOUS element because its first input is help up until it’s joined by an
event on the input before being allowed to pass to the output.
There are two major types of
transistor in the circuit C-element, which are switches and keepers. Switches
are those which contribute to output switching while keepers are those which
used as feedback to hold the state of the output when the logic values of the
input do not match [1].
2.2 Types of C-element
C-elements
distributed into two major types which are static C-element and dynamic
C-element. The types of static C-elements include in this paper are
weak-feedback C-element, conventional C-element and symmetric C-element. The
C-element mostly implemented by using complementary metal-oxide semiconductor
(CMOS). The difference between static C-element and dynamic C-element is the
C-element dynamic C-element has only “switchers” while a static C-element has
additional “keepers” which is a mechanism that provide feedback for memorizing
the output value of the previous stage
if the inputs have different logic value. Hence, minimize the size of keepers
in order to reduce the load in the circuits and limit the race problem.
The
typical application of a conventional C-element is high performance
micropipeline, while weak-feedback C-element commonly used in Caltech
asynchronous microprocessor and the asynchronous ARM with a low-power version
which introduce in Manchester University. The symmetric C-element is often used
in the TANGRAM silicon compiler for
low-power design at Philips Research Laboratories [8].
2.2.1 Dynamic C-elements
Dynamic C-element is the contrast of static
C-element. Basically, it used 6 transistors with the fact that it does not
contain any static storage. When the inputs have different logic values, it
cannot keep its state for unbounded periods [1].
The output of the circuit is
depending on the load on the node C’. The lumped capacitance C0 is equal to the
sum of the capacitances of transistor gate P2 and N2 plus the total wire
capacitance of node C’. Hence, if the voltage of the node C’ is low enough, the
logic value of the output will be ‘0’. While the output logic is ‘1’ when the
voltage of node C’ is sufficiently high. The only factor to effect this voltage
is the resistance RNoff (pull-down network on resistance of the
cut-off nMOS transistor) and RPoff (pull-up network by the
resistance of the cutoff pMOS), which depend on the size of pMOS and nMOS or W
and U. The W and U represent the main body size and the output buffer size.
When the inputs have the different
logic values (A=0 and B=1) or (A=1 and B=0), C’ is either at logic ‘0’ or ‘1’,
depends on the previous state. During this situation, one pMOS and one nMOS
transistors are in active state while their complementary transistors are cut
off.
The output C is a logic value ‘1’,
when RNoff is sufficiently smaller than RPoff it will
pull C’ down and reach the switching threshold of the output inverter.
Conversely, when RPoff is small enough than RNoff to pull
C’ up and this will reach the switching threshold of the output inverter
transfer function. Then, the output will become the logic value ‘0’.
Figure
2.1: CMOS implementation of C-element: Dynamic [5]
2.2.2 Static C-elements
A static circuit utilizes the second PUN (P3 and P4)
and PDN (N3 and N4) with a feedback at the output which P3 and P4 are used to
keep the logic level ‘0’ and N3 and N4 will hold the logic level ‘1’ [9]. When
both inputs are logic ‘0’, then N1 and N2 off and active the P3 and P4 to give
output C will give logic value ‘0’. When both inputs are logic ‘1’, then P1 and
P2 off and active the N3 and N4 to give output C will give logic value ‘1’. When
both inputs are different, there is no transition are activated, hence the P5
or N5 will hold the logic value to output C.
Figure
2.2: CMOS implementation of C-element: Static [7]
Figure
2.3: CMOS implementation of C-element: Static [7]
2.2.3 Weak-feedback (Martin) C-elements
Weak-feedback C-element has been represented by
Martin. The inverter latches are keepers which hold the logic levels of output
when inputs do not match. The feedback inverter must be weak enough to allow
the changes in the state of the latch.
According to Martin, the size of the transistors must follow the
equation below:
Minimum
the sizes of the transistors to reduce the race problem where occur at node
nd0. This is because there is an inherent resistance to switching the state of
the latch. Inherent resistance can reduce but cannot be eliminated. [8]
The correct size for PUN and PDN is
a crucial for them to strong enough to overcome the contention current from the
weak inverter. More, as the VDD is reduced, the PUN, PDN and weak
inverter are being affected, sooner it will cease to operate correctly. [1]
When both ‘A’ and ‘B’ inputs are ‘0’
logic level, the P0 and P1 will conduct and N0 and N1 are turned off. The
circuit will generate a direct path the connection internal nodes at nd0 and VDD.
Hence, the output inverter (P1 and N2) writes ‘0’ to output ‘Q’. The feedback
inverter (P3 and N3) will maintain the output logic value stable ‘1’ to node
nd0 through direct path VDD created by P3.
While when input ‘A’ and ‘B’ are not
the same logic level, there is no connection from internal node nd0 to VDD
or GND. This happens because both P1 and N1 are cut off. The inverter loop, P2
and N2 with P3 and N3 will keep the logic value.
When input ‘A’ and ‘B’ are ‘1’ logic
levels. N1 and N0 will conduct and creating a direct path from node nd0 to GND.
While another direct path from node nd0 to VDD through P3. The
instantaneous short circuit caused by path from VDD to GND through
N1, N0 and P3. Hence, the output inverter will give ‘1’ logic value to output
‘Q’.
Figure
2.4: CMOS implementation of C-element: Weak-feedback [2]
2.2.4 Conventional (Sutherland) C-elements
A conventional C-element is shown in Figure 2.5.
This circuit is invented by Sutherland. The implementation of this circuit is
ratioless means it does not impose any restrictions on the sizes of the
transistors. N1, N2 and N6, the size of W, are the main pull-down transistors
which contribute to output switching. When the inputs do not match, N3, N4 and
N5 give the feedback to hold the state of the output. The bigger the size of
the N3, N4 and N5 will increase the loading effect of the circuits. Hence, the
N3, N4 and N5 made the minimum size to reduce it. Same as N3, N4 and N5, the
transistors P3, P4 and P5 have to use the minimum width. While, P1 and P2 are
the pull-up transistors with the widths of Wp = 2.5 W. [8]
The Sutherland C-elements are switching their
respective outputs, means their feedback inverter is cut-off. When the inputs
are different logic values (A=0 and B=1) or (A=1 and B=0), the transistor P0,
P1, P3 and P4 are turned off, this will prevent any interconnection between
internal node nd0 to VDD. Hence, the output switches to logic ‘0’.
When inputs have the same logic values (A=0 and B=0) or (A=1 and B=1), the
transistors N0, N1, N3 and N4 will be turned off, and this cause the loss
connection between node nd0 and GND. Hence, the output switches to logic ‘1’.
Figure
2.5: CMOS implementation of C-element: Conventional [2]
2.2.5 Symmetric (van-Berkel) C-elements
The Figure 2.6 shows the Symmetric C-element which
is implemented by Van Berkel [7]. Van Berkel topology is the most suited for
C-element implementation for low power and high performance applications [8]. The
Van-Berkel’s circuit is also ratioless, means it is symmetric with respect to
the inputs, same as Sutherland’s circuit. The output state is maintained
through the conducting path of the three transistors in the pull-up tree or the
pull-down tree. The N-tree and P-tree, except the output inverter, must be made
in half size to have the same pull-up and pull-down resistances when switching.
As usual, P3 and N3 must be in minimum size because they are used for feedback
response while N5 and P5 are in normal size to obtain load driving.
When the inputs are different logic values (A=0 and
B=1) or (A=1 and B=0), the transistor P0, P1, P2, P3 and P5 are turned off,
this will prevent any interconnection between internal node nd0 to VDD.
Hence, the output switches to logic ‘0’. When inputs have the same logic values
(A=0 and B=0) or (A=1 and B=1), the transistors N0, N1, N2, N3 and N5 will be
turned off, and this cause the loss connection between node nd0 and GND. Hence,
the output switches to logic ‘1’.
Figure
2.6: CMOS implementation of C-element: Symmetric [2]
2.3 Asynchronous Circuits
The C-element is one of
the primitives that commonly used in asynchronous control circuits. Asynchronous
circuits do not use any periodic clock to integrate the signal thereof the
output changed directly when the changes in the primary data. Asynchronous very large scale integration
(VLSI) is a trend academic research topic to feasible way to solve the problem
of digital VLSI design [10]. Various applications and comparisons revealed that
asynchronous circuits have potential in high-speed, low-power dissipation, low
electromagnetic interference, and a natural match with heterogeneous system
timing. However, its handshake control logic is too large.
Mostly asynchronous circuits are controlled by local
communications, which it only initiates a computation after the previous
computation are complete and it will hold the data before the completion of the
computation. If the computation completed early, then the next computation will
start early. Hence, the asynchronous circuit is faster than synchronous
circuit. The absence of globalization clock avoided with no extra effort during
operation, hence the power dissipation in asynchronous circuit is dramatically
smaller than the synchronous circuit. More, the absence of clock globalization
avoided the clock skew which is same signal transition at different times. This
is because the size in asynchronous decrease and integration levels increase,
then the propagation delay in the wire chips significantly decreases.
Application of asynchronous circuits
such as chip interfaces, bus controller, cache controllers, network
communication controllers, data path components (such as adder, multiplier and
divider), microprocessor (such as CALTECH Asynchronous Microprocessor, NSR
processor, AMULET project and SUN Counter-Flow Processor) [11].
2.3.1 Micropipelines
Micropipelines
are invented by Ivan Sutherland on 1988 in his Turning Award, which
it is used to design the asynchronous circuits [12]. Miropipeline is the
typical asynchronous design, due to its high technique can construct for
high-performance processors. Its basic concept is that use bundle-data channel
implemented with the delay line match to the worst case delay of the single-railed.
Pipelining is a standard way of decomposing operation into concurrently operating stages to increase
throughput at a moderate increase in area. The most common applications used
are digital filters, video compression and general purpose microprocessors and
etc.
Figure 2.7 shows the communication between two
blocks, sender and receiver. When data is ready to send, sender will hold the
data and send a request to receiver. After the receiver receives the data, it
will trigger the acknowledge line to signal that the data is done and free to
change. For increasing the accuracy of the system, the data processing delay is
required so that the request arrives later than the data.
|
Sender
|
|
Reveiver
|
|
Request
|
|
Acknowledgement
|
|
Data
|
Figure
2.7: A bundled data interface
The requirement to control the
micropipelines is C-element [12]. The common logic modules used are XOR gate,
C-element, TOGGLE, SELECT, CALL and ARBITER. XOR act as the OR function while
Muller C-element provides AND function. Starting from the dot, TOOGGLE will
route the output alternatively while SELECT steers the system according to the
logic values of the inputs. CALL
executes the request and demultiplexes the done signal to its corresponding
source. ARBITER will adjudicate two conflicting request.
2.3.1.1 Four-stage FIFO
One of the simplest forms of
micropipeline is FIFO. The Figure 2.8 shows the four stage FIFO. The dash lines
represent the control signal and thick arrows represent the data flow. In the first stage data (Din) is
sent into register (REG) but the data is not valid due to the control wires are
low voltage. Then the data will be valid until the rising transistor in Rin.
After that, the register produces rising transistor on its output terminal (cd)
cause the rising of Ain and r1. The same sequence occurs
in the second stage, which the data in the second register will only valid
until the rising transistor in r1. The data is passed to the
register, then the register will send acknowledgement to the previous register.
At the last register, the data is stored and through Rout to send
data to the customer.
Figure
2.8: Four-stage micropipeline structure [13]
2.4
VLSI
The VLSI (Very Large Scale
Integration) is the technique that coalesces the thousands of transistors into
a single chip, IC (integrated circuit). In designing digital circuits, the design
abstraction level is used and the orders are system, module, gate, circuit and
device as shown in Figure 2.9. The old way designing the chip is manually
twiddling the transistor, nowadays, is using CAD (computer aid design) tools to
grunge the works. With the help of high level CAD tools, the higher level of
abstraction can be done.
Figure
2.9: Design abstraction level. [14]
2.4.1 CMOS
Complementary metal oxide
semiconductor (CMOS) necessitates the fabrication technology hence
complementary and symmetrical PMOS (p-type metal oxide semiconductor) and NMOS
(n-type metal oxide semiconductor) are generated in an IC structure [15].
Figure 2.10 shows the p-type substrate is the basic level of the CMOS. NMOS
transistor is fabricated in p-type silicon subtract at the same time PMOS
transistor is fabricated in n-well region. The pn diode must in reverse-biased
condition with the intention of proper conductive between VDD and VSS.
The basic operation of CMOS is when NMOS is active, PMOS will “off” and vice
versa. This is due to prevent the conductive path between positive and negative
power supplies, hence the circuit can maintain in steady state [15].
Figure
2.10: n-well CMOS structure for forming both NMOS and PMOS
transistors in a single silicon substrate. [15]
Figure 2.11 illustrates the CMOS
inverter with one PMOS transistor and one NMOS transistor. The elimination of
the body effect is done by connecting the respective source (S) of PMOS and
NMOS; this means the VDD is controlling the switching on and off the
transistor, NMOS and PMOS. In Figure 2.11, the source (S) of PMOS, Mp,
is connected to the voltage supply and the source (S) of NMOS, MN,
is connected to the negative power supply or ground or VSS. The
drain (D) of both Mp and Mn are connected to create its
output Vo. The CMOS inverter is functioning in a way that if the
input, Vi, is high (Vi = VDD), PMOS will be
off and NMOS turned on. Therefore, create a path between Vo and
ground, Vo then will show “0” in logic level. When the input is low,
(Vi = 0), the path between VDD and Vo is
created, due to the PMOS is on and NMOS is off. Hence, the output will show “1”
in logic level.
Figure
2.11: CMOS inverter [15]
The threshold voltage (VTN
and VTP) can be obtained through calculation for particular
transistors. The threshold voltage is used to determine the minimum voltage
require for a transistor to function, hence the supply voltage need to be
larger than the threshold voltage for
the proper operation of the transistor. VTN is the threshold voltage
of NMOS and VTP is the threshold voltage of PMOS. VTN can
be attained through Equation 2.3. VTN can be attained through
Equation 2.4. The standard parameters of CMOS are shown in Table 2.1.
VTN
= VTON + ᵧN
[ √(VSBN + 2ϕFN) – √(2ϕFN) ] (2.3)
VTP
= VTOP + ᵧP
[ √(VSBP + 2ϕFP) – √(2ϕFP) ] (2.4)
Table
2.1: CMOS Transistor Parameters
|
Parameters
|
NMOS
|
PMOS
|
|
VTO
|
1V
|
-1V
|
|
ᵧ
|
0.50√(V)
|
0.70√(V)
|
|
2ϕF
|
0.60V
|
0.70V
|
|
K’
|
25µA/V2
|
10µA/V2
|
2.4.1.1 Static CMOS
Static CMOS is the circuit design
that spacious world logic circuits in the world of IC design. Static CMOS
generate output as long as power is supplied, and it requires many
transistors. However, numerous types of static
CMOS have the same properties.
i.
In static CMOS design,
gate output is connected to either VDD or VSS, means
there is no steady path between VDD and VSS.
ii.
The VDD and
VSS are connected to output through a very low resistive, because
CMOS has the advantage of high input impedance and low output impedance.
iii.
The logic value output
of the gates is produced by implementation of Boolean logic. If the logic value
does not matched to the Boolean logic, may there is a transient effect in the
transistors.
iv.
The static power
dissipation in the static CMOS is very low because the current leakage is
small.
2.4.1.1.1 Complementary
CMOS
Complementary CMOS is
one of the examples of static CMOS which is made up by 2 networks, PUN (Pull-up
Network) and PDN (Pull-down Network). PUN only consists PMOS transistor, PDN
consists only NMOS transistors. They are mutually exclusively manner, means
when PUN is on, PDN off and when PDN is on, PUN will off. PUN make connection
between VDD and F when input is in logic level of “1”, in contrast,
PDN make conductive path between ground and F when input is in logic level of
“0”.
Figure
2.12: Complementary CMOS static logic gate [14]
The design rules of
thumb for PUN and PDN networks:
i.
The PUN only made up by
PMOS transistors, PDN is constructed by NMOS transistors.
ii.
The series connection
of NMOS transistors represents the AND function and parallel connection of NMOS
transistors represent the OR function.
iii.
The parallel connection
in PUN corresponds to the series connection in PDN. The series connection in
PUN corresponds to the parallel connection in PDN.
iv.
The number of
transistor requires is 2N, when the PUN has the N number of transistors, PDN
will need to have N number of transistors.
v.
The logic function of
complementary CMOS is proven by using De Morgan’s theorem.
2.4.1.2 Dynamic CMOS
The number of dynamic CMOS is N+2, 2
transistors are act as keepers. Dynamic CMOS is designed to reduce the number
of transistors. It has the advantage of higher speed and lower area
implementation than static CMOS. Due to the number of transistor is decrease,
the load capacitance is getting lower, hence the speed of operation is
increased. However, static power dissipation should be considered in dynamic
CMOS due to the current leakage at the gate. The logic function of dynamic CMOS
is depends on the PDN only. More it is non-ratioed, this implicated the sizing
of Mp is not important. It only consumed dynamic power dissipation
because no static current path in the circuits.
The additional transistors, MP
and Me, are precharge transistor and evaluation transistors. The
switching of precharge and evaluation transistors depend by the CLK input.
Figure
2.13: n-type network [14]
2.4.1.2.1 Precharge
The event of precharge take part when the CLK is 0,
the Mp transistor will Out node precharge to VDD. At the
same time, Me transistor will turned off prevent the conductive path
between VDD and ground. The static power dissipation is eradicated
throughout the precharge period by the appraisal FET.
2.4.1.2.1 Evaluation
When CLK is 1, the evaluation transistor is turned
on. Since MP and Me are exclusive mutual, when evaluation
transistor is turned on, precharge transistor will turned off. The discharging
to the output affected by the input values and pull-down topology. The
precharge value is remained at the capacitance CL. In evaluation
phase, output is connected to the ground and only one transition of the inputs
to the gate. Then the output will discharge before the next precharge operation
and recharge during the precharge process. In evaluation period, when the PDN
is turn off, the output will contains high input impedance. The connection of
input and output are represented in the Equation 2.5 through Boolen’s Logic.
Out =
+ (
) × CLK (2.5)
2.5 Performance of C-element
The Muller C-element can be
evaluated through its performance which is propagation delay, power consumption
and noise immunity. The most common measurements are calculating its speed,
power consumption and energy consumption. The performance of C-elements will be
discussed in this paper to know their propagation delay and power consumption
by using LTSpiceVI. The results are located in Chapter 4.
2.5.1 Speed (Propagation delay)
The
propagation delays of the transistors are depending on the arriving times of
the inputs. According to Sutherland, delay is necessary for correctness of the
operation of circuit, when C-element does not use global clock. There are
commonly delays used in the gates, fundamental mode, speed independent, delay
insensitive and quasi delay insensitive. However, the propagation delay should
be made as small as possible. The lower the propagation delay, the higher the
speed of the circuit.
From the Figure 2.14,
propagation delay can be measured between 50% transition of both input and
output waveforms. The tpLH corresponds to the response time
low-to-high (positive) output transition. The tpHL is the response
time high-to-low (negative) transition. However, the both response time might
be different, hence average propagation delays tp, is defined as the
equation below:
tp = (tpHL + tpLH)/2
(2.6)
The tr and tf represent in the
Figure 2.14 are rise of time and fall of time. The 10% transition of the output
waveform represents the VL while the 90% transition of the output
waveform represents the VH. The 50% transition of the output voltage
is equal to the total transition between VL and VH.
V50%
= (VL + VH)/2
(2.7)
Figure
2.14: Definition of propagation delays and rise and fall times. [14]
The propagation delay is due to the
resistance and capacitance value of the transistor. The higher the capacitance
and resistance value of the transistor, the longer the propagation delay. It
can explain that the propagation delay is directly proportional to the
resistance and capacitance value of the transistor.
2.5.2 Power Consumption
According to Polzer, Steininger and
Lechner as cited in Naffziger et al. (2002) not only low power applications are
needed to concern, however, the power consumption and power dissipation in
clock tree are particularly need to consider in designing a circuit [16].
It is used to determine the amount of energy usage in one operation and the
quantity of the heat that dissipated. Hence, power consumption is a important
factor as it will influence the performance, cost, packing, portability and reliability.
2.5.2.1 Power Dissipation
Market demands for low power
dissipation circuit, C-element which is effectively used in asynchronous
circuits has this advantage. This is because the absent of the globalization
clock causing the reducing in power dissipation of circuits. However, the
present of power dissipation still a challenge in designing circuits. Power
dissipation is divided into two categories dynamic and static power
dissipation. During switching the gate, for dynamic component, the operation of
charging and discharging, the dynamic power is dissipated proportionally to the
switching frequency. More, if the size of the transistor is too large, the
probability occurs the leakage power is high. This is one of the reasons why
the decreasing devices size is important. For static component, static power
dissipation occurs during the gate is static or there is no current activity
and cause the current leakage because the supply is connect to the ground.
2.5.2.2 Dynamic Power Dissipation
The power dissipation
of the C-element is high when the load capacitances increase. The load
capacitance such as wire capacitances and gate capacitances are the majority
loads that will drain the output. Dynamic power dissipation is divided into
three categories switching power, short-circuited power, glitch power and
leakage power. Since the dynamic power consumption is related to the switching
frequency, in the given Equation 2.8,
Pav
= f Cload VDD 2 + f Ishort VDD
+ Ileak VDD (2.8)
Therefore, from the Equation 2.8 can
conclude that the circuit with low power dissipation has the lower speed
operation, when the switching frequency if high.
The switching power
dissipation occurs during the charging and discharging at the output. While,
when the conductive between PMOS and NMOS transistor, or between supply rail
and switching, the short-circuit power consumption transpire. The glitch power
disperses the 15%-20% of the global power. Glitches transpire when there is a
momentarily varies value of output.
2.5.2.3
Power Delay Product (PDP)
The relationship between propagation delay and power
consumption can be related by power delay product (PDP). The power delay
product is one of the measurements that normally used to test the power consumption.
This kind of measurement only calculate the power require when switching the
gate from logic ‘1’ to logic ‘0’ and vice versa. The lower PDP means the time
require to switching the gate is shorter. Hence, the low PDP also means the
speed performance circuit is higher. Equation 2.9
and 2.10 is the calculation of PDP and Equation 2.10 is how the propagation
delay and power consumption of a gate are related.
PDP= (CL VDD2)/2
(2.9)
PDP=
(Pavtp)
(2.10)
Where Pav is the average of
power consumption and tp is the propagation delay.
Through the Equation 2.10, it gives the information about the amount of energy
consumption to perform the basic operation of the circuit.
2.5.2.4
Energy Consumption
Reducing the amount of energy
consumption is the important as energy consumption is one of the most criteria
that will affect to the optimization of output. The energy consumption of the
C-element per output transition depends on the arriving times and order of the
inputs. Energy consumption per output cycle, E is measured
E=
P (VDD)
(2.11)
Where P(VDD) is the average
power extracted from VDD and T is the total period of the output
waveform.
2.5.2.5 Energy Delay Product (EDP)
The energy delay product also kind
of measurements to calculate the energy used in the circuit. EDP somehow has
relevant to the PDP. Equation 2.13 shows the calculation of EDP and relation
between EDP and PDP
EDP = (CL VDD2 tp)/2
(2.12)
= PDP* tp
(2.13)
2.5.3 Noise Performance (Noise Immunity and Noise
Margin)
According to [16], weak feedback
C-element is the least efficient among the other C-elements in noise
performance and consumer the more power in given frequency of 1MHz. While the
conventional C-element in frequency of 1MHz is the less efficient in noise
performance and has the less power consumption among the C-elements. The weak
feedback C-element has the low performance among the implementation of
C-element, but this implementation has the largest frequency range which also
active in low frequency by using less cost area. After comparing, dynamic and
symmetric C-elements have the higher noise immunity than others C-element.
Although dynamic and symmetric C-element has the higher performance than
others, their frequency range is the lowest among the circuits. Dynamic
C-element has the lower performance but it has the greatest frequency range.
Figure
2.15: Voltage transfer characteristics [13]
Figure
2.16: Voltage levels and logic state relationship of Figure 2.15 [13]
In Figure 2.16, VL is the nominal voltage
corresponding to a low-logic state at the output of a logic gate for vI =
VH. VH is the
nominal voltage corresponding to a high-logic state at the output of a logic
gate for vI = VL. VIL also known as low input
logic level represents the maximum input voltage. While, VIH
represent the minimum input voltage which also known as high input logic level.
VOH and VOL is the output voltage corresponding to an
input voltage of VIL and an output voltage VIH
respectively.
In Figure 2.16, the noise margin in the high state
(NMH) and the noise margin in the low state (NML) are the
“safety margins”. NMH and NML are the regions that
prevent the gate from producing erroneous logic decisions in the presence of
noise source. Noise margins are used to absorb the voltage difference between
input and output voltage and also absorb the parameter variance that occurs in the
logic gate. Meanwhile, the higher the noise margin of a circuit will have
greater the performance and efficiency.
2.6 Parameters of C-element
The
parameters are consider in this papers are transistor sizing, supply voltage
and load capacitance.
2.6.1 Transistor Sizing
The propagation delay can be
decreased by reducing the output capacitance and resistance in the transistors.
The resistance and capacitance is inversely proportional to the W/L ratio of
the device. However, the transistors of static C-elements are divided into
switchers and keepers. The switchers are main transistors which needed to large
enough to overcome the contentional current from the keepers. For pull-up main
transistor, normally is factor of 2.5 to the pull-down transistor. Hence it is
important to understand which transistors are belonging to switchers (main
transistors) or keepers.
In symmetric C-element, N3 and P3
are the keeper transistors while P4 and N4 are output inverters. The
conventional C-element, the keeper transistors are N3, N4, N5, P3, P4 and P5,
but P2 and N2 are output inverters. The weak feed-back C-element, it’s keepers
are N3 and P3 which is also the weak-feedback inverter, but the output inverter
is P2 and N2 which need to larger than it’s weak inverter. However, the output
inverters of dynamic C-element are P2 and N2 and it does not have keeper
transistor.
2.6.2 Supply voltage
The
higher the supply voltage, the faster the evaluation however the voltage supply
is directly proportional to the power consumption of the circuits. If the
voltage supply is half, the total power consumption will be halve to.
2.6.3 Load Capacitors
Load capacitor is used to fine tune
the simulation of output, however, it is necessary to be as small as possible.
This is due to the load capacitor will drag the evaluation time of the output.
2.6.4 Threshold Voltage
According
[17], there are types of threshold voltages for C-element, which are
low-to-high threshold voltage, VTH and high-to-low threshold voltage
VTL. VTH is the minimum input voltage that cause the
output switches from low to high, while VTL is the maximum input
voltage which can make the outputs from high to low. The output may oscillate
and produce extra data to the full-buffer circuit when the VTL is
greater than VTH. The well-order threshold voltage still cannot
guarantee the proper comportment of the full buffer. This is because if one of
the internal nodes in full-buffer circuit has greater capacitance than others,
it not only causing the increasing of propagation delay but also stalls the
handshaking process. The large capacitance and delays will happen mostly
because the wire is longer than others.
Low
voltage circuits, operating in the near-threshold region, provide one of the
best trade-offs between power consumption and performance in low power
applications [18]. According to [19], the lower threshold voltage in PMOS
device has the higher robustness with regards to soft errors.
2.7
Issues of C-elements
Issues
of C-element have to be considering when designing the circuits. This is due to
these issues are the factors will affect and drag the output of C-element.
2.7.1 Loading Effect
When there is vary of
output voltage with the according to the electrical current means there is loading effect in the system. Loading
effect will cause the correctness of the output may deviate. Hence there is
necessary to minimal the size of keepers to prevent their loading effect in the
transistors. Loading effect commonly divided into two types, that is inter
element loading and process loading. Inter element loading is when adding a new
element into the circuit, it changes the characteristic of the previous
element. While process element occurs when the system is measured during the process,
the sensing element causes the value of variable to change.
2.7.2 Race Problem
Race problem occurs because there is an inherent
resistance in the node C’. Race problem in node C’ of weak-feedback C-element
cannot be eliminated but can be reduced by increasing the length of the
transistor. However, the increasing the size of the transistor will increase
the load of the output and cause the node C’ more liable by noise.
CHAPTER 3
METHODOLOGY
3.1
Introduction
The
design techniques and tools used for this project will be discussed in this
chapter. This chapter emphasizes on the circuit simulation and result
compiling. The flow chart about step taken for overall project, circuit
designing and circuit simulation will be shown. The design overview of the
dynamic C-element, conventional C-element, symmetric C-element and
weal-feedback C-element will be shown in this chapter. Design and simulate of
the C-elements by using LTSpice VI to obtain propagation delay and power
consumption. Various techniques and theories are applied during designing
process in order to attain the best performance C-element.
3.2 Flow Chart
Once confirm the topic, investigation and analytic the type of C-element to use in this paper is carried out. Determine the difference of each C-element in terms of their layout and characteristics. Figure 3.1 shows the process flow of project overall.
|
Start
|
|
End
|
|
Understanding project title and requirement
|
|
Compile the data and circuit for simulation
|
|
Investigate and compare each type of C-elements
|
|
Meet supervisor to review the information
|
|
Circuit simulation
|
|
Understanding circuit simulation software and
technique
|
|
Understanding project title and requirement
|
|
Troubleshooting
|
|
Correct information
|
|
Error
|
|
No Error
|
|
Figure 3.1: Project overall flow chart
|
3.3 Simulation Circuit using LTSpice VI
After
determine the factors that could affect the performance of the circuits, the
four simulation circuits are drawn by using LTSpice VI based on Figures3.4,
Figure 3.5, Figure 3.6 and Figure 3.7. The factors represented by the
parameters which are ratio of
[(Wp/Lp)/(Wn/Ln)], supply voltage
and load capacitors. Figure
3.2 shows the process flow of designing the C-element and Figure 3.3 shows the
process flow of simulating the C-element.
|
Start
|
|
Research on the simulation software to be used
|
|
Drawing the desired circuit using the simulation
software
|
|
Data collection and analysis
|
|
Simulation on the circuits to be compared
|
|
Manipulating variables based on comparison table
|
|
Circuit test run for error check
|
|
End
|
|
No
|
|
Yes
|
|
Figure 3.2: The circuit designing and simulation
of circuit flow chart
|
|
Start
|
|
End
|
|
Analysis circuit layout, description and
properties
|
|
Plot schematic diagram using LTSpice VI
|
|
Investigate the suitable parameters used for
circuit simulation
|
|
Determine the parameters for simulation
|
|
Circuit simulation
|
|
Analysis their performance in terms of speed and
power consumption
|
|
Troubleshooting
|
|
Error
|
|
No error
|
|
Figure 3.3: The result simulation and analysis
C-element flow chart
|
Figure 3.4: Schematic diagram of Dynamic C-element
Figure 3.5: Schematic diagram of Conventional
C-element
Figure 3.6: Schematic diagram of Symmetric C-element
Figure 3.7: Schematic diagram of Weak-feedback
C-element
3.3.1 Circuit
Description
All
circuits are drawn and simulated by using LTSpiceIV. The all layout of
C-element will be saved after the simulation is completed. Make sure no error
exist before the simulation. VDD represent the supply voltage and CL
will represent the load capacitance. The supply voltage is connected to the DC
voltage supply while the input A and B will connect to the PULSE voltage. The
pulse voltage is needed to determine before the simulation of the C-element.
Table 3.1 illustrate the pulse voltage parameters used in all circuits.
Table 3.1: Pulse voltage parameters
|
Parameters
|
VA
|
VB
|
|
Initial Voltage (V initial)
|
0V
|
0V
|
|
Peak Voltage (Von)
|
1V
|
1V
|
|
Delay Time (T delay)
|
1ns
|
0
|
|
Rise Time (T rise)
|
0.1ns
|
0.1ns
|
|
Fall Time (T fall)
|
0.01ns
|
0.01ns
|
|
Pulse Width (T on)
|
10
|
10
|
|
Pulse Period (T period)
|
20
|
20
|
|
Number of Cycles (N cycle)
|
5
|
5
|
3.4 Circuit
Layout
The
project flow after the simulating and comparison of the performance among the
C-elements are completed is shown in Figure 3.8. Once the parameters and the
stick diagrams are set for all C-elements, the layout of the C-elements are
drawn by using Microwind. Designing the layout of C-elements are drawn
according to the rules in Table 3.2.Use DRC (Design Rule Checker) to check the
error of the layout.
|
Figure 3.8: Process overflow after the simulating
of the C-element
|
|
Start
|
|
End
|
|
Determine the smallest area size
|
|
Draw Euler Path and Stick Diagram
|
|
Circuit layout of each C-element
|
|
Comparison of the area size of each C-element
|
|
Investigating the application for the C-element
|
|
Troubleshooting
|
|
Error
|
|
No Error
|
|
Determine the parameters
|
|
Collecting the information and list all the
application
|
Table 3.2: Minimum width requirement for different configuration
[20]
|
Minimum Width Requirement
|
Figure Representative
|
|
N-Well
r101 Minimum well size 12λ
r102 Between wells 12λ
r110 Minimum well area
144 λ2
|
|
|
Diffusion
r201 Minimum N+ and P+
diffusion width 4 λ
r202 Between two P+ and N+
diffusions 4 λ
r203 Extra nwell after P+
diffusion 6 λ
r204 Between N+ diffusion
and nwell 6 λ
r205 Border of well after N+
polarization 2 λ
r206 Between N+ and P +
polarization 0 λ
r207 Border of nwell for P+
polarization 6 λ
r210 Minimum diffusion area
24 λ2
|
|
|
Polysilicon
r301 Polysilicon width 2 λ
r302 Polysilicon gate on diffusion 2 λ
r303 Polysilicon gate on diffusion
for high voltage
MOS 4 λ
r304 Between two polysilicon
boxes
3 λ
r305 Polysilicon vs. other
diffusion 2 λ
r306 Diffusion after polysilicon 4 λ
r307 Extra gate after polysilicon 3 λ
r310 Minimum surface 8 λ2
|
|
|
2nd Polysilicon
r311 Polysilicon2 width 2 λ
r312 Polysilicon2 gate on diffusion 2 λ
r320 Polysilicon2 minimum surface
8 λ2
|
|
|
MOS option
rOpt Border of “option” layer over
diff N+ and
diff P+
7 λ
|
|
|
Contact
r401 Contact width 2 λ
r402 Between two contacts 5 λ
r403 Extra diffusion over contact 2 λ
r404 Extra poly over contact 2 λ
r405 Extra metal over contact 2 λ
r406 Distance between contact and
poly gate 3 λ
r407 Extra poly2 over contact 2 λ
|
|
|
Metal 1
r501 Metal width 4 λ
r502 Between two metals 4 λ
r510 Minimum surface 16 λ2
|
|
|
Metal 2
r701 Metal2 width 4 λ
r702 Between two metal2s 4 λ
r710 Minimum surface 16 λ2
|
|
3.5 Parameters
Analysis
Parameters used for analysis are width over ratio [(Wp/Lp)/(Wn/Ln)], the technology used in circuit layout, the supply
voltage VDD and the load capacitance CL. The result will
compile and compare the performance through the propagation delay and power
consumption. The highest performance will be determined through the shortest
propagation delay and lowest power consumption. Propagation delay will be
determined according to the Equation 2.6.
3.5.1 Transistor
Sizing Analysis
This
analysis will conduct to find the optimum transistor sizing for each
C-elements. Transistor size is one of the crucial parameters in designing high
performance circuit. The value will be vary based on the 1λ unit (0.125µm) from the ratio of [(Wp/Lp)/(Wn/Ln)]
equal 2, 2.5 and 3 for switches and ratio of
[(Wp/Lp)/(Wn/Ln)] from 2, 2.5 and 3 for keepers. The common and
growing DSM technology, which is length 65nm, 45nm, 32nm, 22nm, and 14nm are used for analysis. The
size of main transistors needs to be twice bigger than the output inverters for
all types of C-element except the feedback inverter in weak-feedback inverter
C-element.
Size main transistor = 2 size of output inverter
(3.1)
The size of switchers needs to be at least 2r bigger
than the weak-feedback inverter.
(W/L)main transistor > 2r (W/L) feed-back
inverter (3.2)
The
technology of length is referred through these years recently as shown in the
Figure 3.9.
Figure 3.9: Technology (nm) from year 2006 until 2014
Table 3.3:
Setting for Transistor Sizing Analysis with 65nm Technology for Dynamic,
Conventional and Symmetric C-element.
|
Ratio
|
Switches
|
Keepers
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
|||
|
2
|
1.300
|
0.650
|
0.500
|
0.325
|
50
|
1
|
|
2.5
|
1.625
|
0.650
|
0.8125
|
0.325
|
50
|
1
|
|
3
|
1.950
|
0.650
|
0.975
|
0.325
|
50
|
1
|
Table 3.4:
Setting for Transistor Sizing Analysis with 45nm Technology for Dynamic,
Conventional and Symmetric C-element.
|
Ratio
|
Switches
|
Keepers
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
|||
|
2
|
0.900
|
0.450
|
0.450
|
0.225
|
50
|
1
|
|
2.5
|
1.125
|
0.450
|
0.5625
|
0.225
|
50
|
1
|
|
3
|
1.350
|
0.450
|
0.675
|
0.225
|
50
|
1
|
Table 3.5:
Setting for Transistor Sizing Analysis with 32nm Technology for Dynamic,
Conventional and Symmetric C-element.
|
Ratio
|
Switches
|
Keepers
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
|||
|
2
|
0.640
|
0.320
|
0.320
|
0.160
|
50
|
1
|
|
2.5
|
0.800
|
0.320
|
0.400
|
0.160
|
50
|
1
|
|
3
|
0.960
|
0.320
|
0.480
|
0.160
|
50
|
1
|
Table 3.6:
Setting for Transistor Sizing Analysis with 22nm Technology for Dynamic,
Conventional and Symmetric C-element.
|
Ratio
|
Switches
|
Keepers
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
|||
|
2
|
0.440
|
0.220
|
0.220
|
0.110
|
50
|
1
|
|
2.5
|
0.550
|
0.220
|
0.275
|
0.110
|
50
|
1
|
|
3
|
0.660
|
0.220
|
0.330
|
0.110
|
50
|
1
|
Table 3.7:
Setting for Transistor Sizing Analysis with 14nm Technology for Dynamic,
Conventional and Symmetric C-element.
|
Ratio
|
Switches
|
Keepers
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
|||
|
2
|
0.280
|
0.140
|
0.140
|
0.007
|
50
|
1
|
|
2.5
|
0.350
|
0.140
|
0.175
|
0.007
|
50
|
1
|
|
3
|
0.420
|
0.140
|
0.210
|
0.007
|
50
|
1
|
Table 3.8:
Setting for Transistor Sizing Analysis with 65nm Technology and r = 1 for Weak
feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
1.300
|
0.650
|
0.500
|
0.325
|
1
|
50
|
1
|
|
2.5
|
1.625
|
0.650
|
0.8125
|
0.325
|
1
|
50
|
1
|
|
3
|
1.950
|
0.650
|
0.975
|
0.325
|
1
|
50
|
1
|
Table 3.9:
Setting for Transistor Sizing Analysis with 65nm Technology and r = 1.25 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
1.300
|
0.650
|
0.500
|
0.325
|
1.25
|
50
|
1
|
|
2.5
|
1.625
|
0.650
|
0.8125
|
0.325
|
1.25
|
50
|
1
|
|
3
|
1.950
|
0.650
|
0.975
|
0.325
|
1.25
|
50
|
1
|
Table 3.10:
Setting for Transistor Sizing Analysis with 65nm Technology and r = 1.5 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
1.300
|
0.650
|
0.500
|
0.325
|
1.5
|
50
|
1
|
|
2.5
|
1.625
|
0.650
|
0.8125
|
0.325
|
1.5
|
50
|
1
|
|
3
|
1.950
|
0.650
|
0.975
|
0.325
|
1.5
|
50
|
1
|
Table 3.11:
Setting for Transistor Sizing Analysis with 45nm Technology and r = 1 for Weak
feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.900
|
0.450
|
0.450
|
0.225
|
1
|
50
|
1
|
|
2.5
|
1.125
|
0.450
|
0.5625
|
0.225
|
1
|
50
|
1
|
|
3
|
1.350
|
0.450
|
0.675
|
0.225
|
1
|
50
|
1
|
Table 3.12:
Setting for Transistor Sizing Analysis with 45nm Technology and r = 1.25 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.900
|
0.450
|
0.450
|
0.225
|
1.25
|
50
|
1
|
|
2.5
|
1.125
|
0.450
|
0.5625
|
0.225
|
1.25
|
50
|
1
|
|
3
|
1.350
|
0.450
|
0.675
|
0.225
|
1.25
|
50
|
1
|
Table 3.13:
Setting for Transistor Sizing Analysis with 45nm Technology and r = 1.5 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.900
|
0.450
|
0.450
|
0.225
|
1.5
|
50
|
1
|
|
2.5
|
1.125
|
0.450
|
0.5625
|
0.225
|
1.5
|
50
|
1
|
|
3
|
1.350
|
0.450
|
0.675
|
0.225
|
1.5
|
50
|
1
|
Table 3.14:
Setting for Transistor Sizing Analysis with 32nm Technology and r = 1 for Weak
feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.640
|
0.320
|
0.320
|
0.160
|
1
|
50
|
1
|
|
2.5
|
0.800
|
0.320
|
0.400
|
0.160
|
1
|
50
|
1
|
|
3
|
0.960
|
0.320
|
0.480
|
0.160
|
1
|
50
|
1
|
Table 3.15:
Setting for Transistor Sizing Analysis with 32nm Technology and r = 1.25 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.640
|
0.320
|
0.320
|
0.160
|
1.25
|
50
|
1
|
|
2.5
|
0.800
|
0.320
|
0.400
|
0.160
|
1.25
|
50
|
1
|
|
3
|
0.960
|
0.320
|
0.480
|
0.160
|
1.25
|
50
|
1
|
Table 3.16:
Setting for Transistor Sizing Analysis with 32nm Technology and r = 1.5 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.640
|
0.320
|
0.320
|
0.160
|
1.5
|
50
|
1
|
|
2.5
|
0.800
|
0.320
|
0.400
|
0.160
|
1.5
|
50
|
1
|
|
3
|
0.960
|
0.320
|
0.480
|
0.160
|
1.5
|
50
|
1
|
Table 3.17:
Setting for Transistor Sizing Analysis with 22nm Technology and r = 1 for Weak
feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.440
|
0.220
|
0.220
|
0.110
|
1
|
50
|
1
|
|
2.5
|
0.550
|
0.220
|
0.275
|
0.110
|
1
|
50
|
1
|
|
3
|
0.660
|
0.220
|
0.330
|
0.110
|
1
|
50
|
1
|
Table 3.18:
Setting for Transistor Sizing Analysis with 22nm Technology and r = 1.25 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.440
|
0.220
|
0.220
|
0.110
|
1.25
|
50
|
1
|
|
2.5
|
0.550
|
0.220
|
0.275
|
0.110
|
1.25
|
50
|
1
|
|
3
|
0.660
|
0.220
|
0.330
|
0.110
|
1.25
|
50
|
1
|
Table 3.19:
Setting for Transistor Sizing Analysis with 22nm Technology and r = 1.5 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.440
|
0.220
|
0.220
|
0.110
|
1.5
|
50
|
1
|
|
2.5
|
0.550
|
0.220
|
0.275
|
0.110
|
1.5
|
50
|
1
|
|
3
|
0.660
|
0.220
|
0.330
|
0.110
|
1.5
|
50
|
1
|
Table 3.20:
Setting for Transistor Sizing Analysis with 14nm Technology and r = 1 for Weak
feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.280
|
0.140
|
0.140
|
0.007
|
1
|
50
|
1
|
|
2.5
|
0.350
|
0.140
|
0.175
|
0.007
|
1
|
50
|
1
|
|
3
|
0.420
|
0.140
|
0.210
|
0.007
|
1
|
50
|
1
|
Table 3.21:
Setting for Transistor Sizing Analysis with 14nm Technology and r = 1.25 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.280
|
0.140
|
0.140
|
0.007
|
1.25
|
50
|
1
|
|
2.5
|
0.350
|
0.140
|
0.175
|
0.007
|
1.25
|
50
|
1
|
|
3
|
0.420
|
0.140
|
0.210
|
0.007
|
1.25
|
50
|
1
|
Table 3.22:
Setting for Transistor Sizing Analysis with 14nm Technology and r = 1.5 for
Weak feed-back C-element.
|
Ratio
|
Switches
|
Keepers
|
r
|
CL (fF)
|
VDD
|
||
|
Wp (µm)
|
Wn (µm)
|
Wp (µm)
|
Wn (µm)
|
||||
|
2
|
0.280
|
0.140
|
0.140
|
0.007
|
1.5
|
50
|
1
|
|
2.5
|
0.350
|
0.140
|
0.175
|
0.007
|
1.5
|
50
|
1
|
|
3
|
0.420
|
0.140
|
0.210
|
0.007
|
1.5
|
50
|
1
|
3.4.2 Supply
Voltage Analysis
Optimum
voltage will be analysis by manipulating various supply voltage in range
between 1V, 2.5V and 5V. According to theory, if supply voltage is increase,
the power consumption will also increase. However, if the supply voltage is
low, the noise immunity of the circuit is reduced and the evaluation time will
also decrease. During the simulation, the DC voltage input and another two
source voltage need to be set same value. When simulating other variables, 1V
is used as the input voltage.
Table 3.23:
Setting for Supply Voltage Analysis for C-element.
|
Supply Voltage (V)
|
Technology (nm)
|
CL (fF)
|
r
|
|
1
|
65
|
50
|
1
|
|
45
|
|||
|
32
|
|||
|
22
|
|||
|
14
|
|||
|
2.5
|
65
|
50
|
1
|
|
45
|
|||
|
32
|
|||
|
22
|
|||
|
14
|
|||
|
5
|
65
|
50
|
1
|
|
45
|
|||
|
32
|
|||
|
22
|
|||
|
14
|
3.4.2 Load
Capacitance Analysis
Setting
load capacitance as variable in range between 50fF, 75fF and 100fF. 50fF is
chosen when investigating other variables.
Table 3.24:
Setting for Load Capacitance Analysis for C-element.
|
CL (fF)
|
Technology (nm)
|
Supply Voltage (V)
|
r
|
|
50
|
65
|
1
|
1.25
|
|
45
|
|||
|
32
|
|||
|
22
|
|||
|
14
|
|||
|
75
|
65
|
1
|
1.25
|
|
45
|
|||
|
32
|
|||
|
22
|
|||
|
14
|
|||
|
100
|
65
|
1
|
1.25
|
|
45
|
|||
|
32
|
|||
|
22
|
|||
|
14
|
